逻辑
RS1G175-Q1
The RS1G175-Q1 single D-type flip-flop is designed for 1.65V to 5.5V VCC operation. The RS1G175-Q1 device has an asynchronous clear (CLR̅̅̅̅̅) input. When CLR̅̅̅̅̅ is high, data from the input pin (D) is transferred to the output pin (Q) on the clock's (CLK) rising edge. When CLR̅̅̅̅̅ is low, Q is forced into the low state, regardless of the clock edge or data on D
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