The RS1G74-Q1 single positive-edge-triggered D-type flip-flop is designed for 1.65V to 5.5V VCC operation. A low level at the preset (PRE̅̅̅̅̅̅) or clear (CLR̅̅̅̅̅) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE̅̅̅̅̅̅ and CLR̅̅̅̅̅ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.